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Standard Products
PWM5031 RadHard High Speed PWM Controller
www.aeroflex.com/Power August 2, 2005
FEATURES

Radiation Hardness: - Total Dose 1MRad(Si) - Single Event Upset (SEU) 100MeV-cm2 /mg CMOS Low Power Design Sleep & Enable Control Lines Optimized for Applications: Buck, Boost, Flyback, Forward and Center Tapped Push-Pull Converters Supports Current Mode or Voltage Mode Operations Selectable 50% / 100% Duty Cycle Under-Voltage Lockout with Hysteresis Dual 1Amp Peak Totem Pole Outputs 1 MHz Maximum - User Selectable Low RO Error Amp Auxiliary Op Amp with Shut Down Pin Power OK Indicator Designed for Commercial, Industrial and Aerospace Applications Ceramic 24-Gull lead, Hermetic Package, .6L x .3W x .13H - Contact Factory for Die Availability DSCC SMD Pending
NOTE: Aeroflex Plainview does not currently have a DSCC Certified Radiation Hardened Assurance Program Developed in Partnership with JHU/APL and the Technology Application Group for the Mars Technology Program; Part of NASA's Mars Exploration Program
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OVERVIEW AND GENERAL OPERATION
The chip is a fixed frequency Pulse Width Modulator based on the industry standard UC1843x Series with significant enhancements in performance and functionality. The chip operates in either the voltage or current mode and can support a wide variety of converter topologies. Radiation hardened by design techniques ensure the chip's outstanding radiation tolerance (>1MRads) while reducing operating current by more than an order of magnitude over comparable parts. The PWM5031 provides an under voltage lockout feature with hysteresis that also provides an output to indicate Power is OK. An input called Sleep is used to power down the entire chip, the Enable input is used to shut down the Oscillator / Output Drives, and the Soft input drives the Output to zero. There is also a signal input called ENAUX that is used to disable the output to the auxiliary op-amp. The dual output drivers are designed using a Totem Pole output capable of sinking and sourcing 50mA constant current and peak currents up to 1 Amp to support a large variety of Power MOSFETs. Additional features that boost the appeal and utility of the part are: Dual break-before-make Totem Pole output stage is employed that virtually eliminates cross conduction and current shoot through Logic level input that allows the user to select either 50% or 100% maximum duty cycle operation Improved oscillator stage that vastly increases waveform linearity and reduces output voltage error Uncommitted on-board op-amp which can be used for signal conditioning, pulse feedback, or any other user defined purpose
SCD5031 Rev B
VREF 11
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VCC 1,24 Reference Internal Bias Internal Enable / Shutdown Control Logic & Control Functions Oscillator
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PWROK SLEEP 10 3 EN 17 50% 2 DRVP 18,19
Undervoltage Lockout
OUTA 21
Cset Rset
8 9
Duty Cycle Limiting (50% or 100%) Output Drive
SOFT Comp
7 4
VFB
Current Sense Comparators 5 S 1.4V Error Amp R Q Q OUTB 20
Isense 6 Uncommited Op-Amp
1V
12 VEE
15 AOUT
16 14 ENAUX PIN
13 NIN
22, 23 DRVN
FIGURE 1 - Block Diagram
SCD5031 Rev B
2
PWM5031 PWM PIN DESCRIPTION
PIN # 1 24 SIGNAL NAME VCC Logic Power Input selects maximum duty cycle (50% or 100%). Logic ''1'' selects 50% max duty cycle and Output B is the complement of Output A. Logic ''0'' selects 100% and Output A is in-phase with Output B. FUNCTION DESCRIPTION
2
3 4 5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
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50% SLEEP COMP VFB Negative Input to the error amplifier ISENSE Input Current sense pin used for current mode control SOFT CSET RSET PWROK VREF VEE NIN PIN AOUT ENAUX EN Buffered 3V Output reference voltage Logic Ground Auxiliary Op-Amp Inverting Input Auxiliary Op-Amp Non-Inverting Input Auxiliary Op-Amp Output Input Enable of Auxiliary Op-Amp (Active Hi)
This Input shuts down all functions on chip when asserted (Active Hi) Output of the error amplifier. Place compensation network from this pin to VFB to stabilize converter.
This High impedance Input is used to limit the error amplifier output voltage. Applying an RC circuit to this pin provides the standard softstart function. Pull the pin to ground to force zero duty cycle.
Works with Rset to establish oscillator free running frequency. Place cap from this Input pin to ground. Can synchronize oscillator by overdriving this pin with an external frequency source. Works with Cset to establish oscillator free running frequency. Place resistor from this Input pin to ground. Logical output of UV lockout circuit -- logic ''1'' indicates chip has valid Vcc
Logic Input that enables the oscillator and output drivers. Reference voltage remains valid (Active Hi). Output stage negative rail Totem pole Output B Totem pole Output A Output stage positive rail
DRVN OUT B OUTA DRVP
SCD5031 Rev B
3
ABSOLUTE MAXIMUM RATINGS1
Junction Temperature Range Storage Temperature Range VCC & DRVP Supply Voltages Steady State Output Current -55C to +150C -65C to +150C 7.0VDC 50 mA 1.0 A
Peak Output Current (Internally Limited) Analog Inputs (Pins 5, 6, 13, 14)
Power Dissipation at TA = +25C
Lead Temperature (soldering, 10 seconds)
Note 1: All voltages are with respect to Pin 12. All currents are positive into the specified terminal.
PARAMETER
DC Operating Voltage Quiescent Current
Output Drive Voltage
Output Duty Cycle - Maximum 50% Pin = Logic 0 50% Pin = Logic 1 Thermal Resistance TJC Sleep Mode
* Dependent on Value of CSET & Operating Frequency
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OPERATING CONDITIONS
CONDITION SYMBOL VCC ICC MIN 4.5 SLEEP @ '0'; EN & ENAUX @ '1' DRVP -
VEE - 0.5V to VCC + 0.5V 500mW 300C
TYP 5.0 -
MAX 5.5 4.0 5.0 50 6.0 20
UNIT V mA V % % C/W A
-
100% Duty Cycle 50% Duty Cycle -
97* -
ICCS
ELECTRICAL CHARACTERISTICS
4.5 V < Vcc < 5.5V, -55C < TA < +125C, unless otherwise specified PARAMETER Reference Section Reference Voltage Line Regulation Load Regulation Thermal Regulation Output Short Circuit Oscillator Section Frequency Range Frequency Stability (Part to Part) Temperature Stability RSET Range CSET Range
SCD5031 Rev B
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TA = 25C, IO = -1 mA
2.95 -
3.05 .1 .05 1 -
3.15 -40
V % % % mA
0 < IO < 25 mA
-
Note 2
-
Note 2 Note 2 TMIN < TA < TMAX (Note 2) Note 2 Note 2
4
20 50 -
1.5 0.5 -
1,000 2 1 600
KHz % % K pF
ELECTRICAL CHARACTERISTICS con't
4.5 V < Vcc < 5.5V, -55C < TA < +125C, unless otherwise specified PARAMETER Error Amp Section Input Offset Voltage TEST CONDITIONS MIN TYP MAX UNITS
Input Common Mode Voltage Range Input Bias Current
Open Loop Voltage Gain (AVOL) Unity Gain Bandwidth
Power Supply Rejection Ratio (PSRR) Output Sink Current
Output Source Current
VOUT High (Limited by VSOFT) VOUT Low
Current Sense Section Input Offset Voltage
Common Mode Input Voltage Input Bias Current ISENSE to Output Delay Output Section
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Note 2 Note 2 VEE + 0.2 Note 2 Note 2 100 1.0 60 Note 2 Note 2 VFB = 3.0V, VSOFT = 1.1V VFB = 2.0V, VSOFT = 5V VFB = 2.0V, RL = 15K to GND VFB = 3.0V, RL = 15K to +5V VSOFT 0.2 Note 2 VSOFT = 5V, Note 2 & 3 Note 2 0.1 ISINK = 1.0mA 4.9 4.7 TA = 25C, CL = 1.0nF TA = 25C, CL = 1.0nF ISINK = 50mApk ISOURCE = 1.0mA, DRVP = 5V ISOURCE = 50mApk, DRVP = 5V
2.0 -
3.3 VCC - 0.2 -1.0 +62 -40 VEE + 0.2
mV V A dB MHz dB mA mA V V
80
3.3 1.0 1.0 100
mV V A ns
1.35 50 8.0 6.0
0.1 0.3 -
V V V V A mA ns ns
Output Low Level
Output High Level
Peak Output Current Steady State Output Current Rise Time Fall Time
SCD5031 Rev B
5
ELECTRICAL CHARACTERISTICS con't
4.5 V < Vcc < 5.5V, -55C < TA < +125C, unless otherwise specified PARAMETER Auxiliary Amp Section Input Offset Voltage TEST CONDITIONS MIN TYP MAX UNITS
Input Common Mode Voltage Range Input Bias Current AVOL
Unity Gain Bandwidth PSRR
Output Sink Current
Output Source Current VOUT High VOUT Low
Under-Voltage Lockout Section Start Threshold
Operating Voltage After Turn On, Min. Digital Inputs VIL VIH Leakage Current - IIN Digital Ouput (PWROK) VOL VOH
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Off VEE or VCC Rail, Note 2 Note 2 VEE + 0.2 f = 40KHz, 2V < VO < 4V, Note 2 Note 2 100 1.0 60 4.5V < VCC < 5.5V, Note 2 VPIN < VNIN, ENAUX = Hi VPIN > VNIN, ENAUX = Hi VPIN > VNIN, ENAUX = Hi VCC - 0.2 VPIN < VNIN, ENAUX = Hi 4.0 3.4 Logic Low Logic High 2.0 Logic low at 1.6mA Logic high at -1.6mA VCC - 0.6
70 -
3.5 VCC - 0.2 1.0 +80 -50 VEE + 0.2
mV V A dB MHz dB mA mA V V
4.1 3.5
4.25 3.65
V V
-
0.8 100
V V nA
-
VEE + 0.3 -
V V
Note 2. Parameters are guaranteed by design, not tested. Note 3. Parameter measured at trip point of latch with VFB = 0.
SCD5031 Rev B
6
DETAILED COMPONENT OPERATION AND PERFORMANCE POWER SUPPLIES
Three I/O pins are used to supply power to the chip: 1) Two DRVP (referenced to DRVN) for the output stage. 2) VCC (referenced to VEE) for all other functions. VCC and DRVP are at 5V 10%. The two supplies are routed from separate pins to prevent power stage switching spikes from interfering with the chip's other circuits. VCC is specified to draw a maximum of 4.0mA under normal operating conditions. For protection against inadvertent over/undervoltages, the chip's input pins are diode clamped to the supply rails through current limiting resistors.
Undervoltage Lockout
The chip includes an internal undervoltage lockout circuit with built in hysteresis and a logic level power good indicator. The positive and negative going thresholds are nominally 4.1V and 3.5V, respectively. If Vcc is below this range, the oscillator, error amplifier, main comparators, and output drive circuits are all disabled. The power OK indicator is active high (logic ''1'') when a valid supply voltage is applied.
POWER OK 1
ICC
Vcc
24
ON/OFF COMMAND TO REST OF IC 1.6mA Von Voff 4.1V 3.5V
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VOFF VON
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VCC
FIGURE 2 -Undervoltage Lockout Shutdown Logic
The chip has two logic level inputs for implementing shutdown functions. Asserting a logic ''1'' on the SLEEP pin disables all chip functions and puts the chip into a very low power consumption mode. Asserting a logic ''0'' on the EN pin shuts down all functions except the reference, bias generators, and auxiliary amplifier.
INPUTS Sleep 0 0 0 0 1 1 1 1 EN 0 0 1 1 X X X X ENAUX 0 1 0 1 X X X X OUTA&B 0 0 Active Active 0 0 0 0 AOUT 0 Active 0 Active 0 0 0 0
OUTPUTS COMP 0 0 Active Active 0 0 0 0 PWROK Active Active Active Active 0 0 0 0 Vref 3 VDC 3 VDC 3 VDC 3 VDC 0 0 0 0
Truth Table
SCD5031 Rev B
7
OSCILLATOR
The chip uses two precision current mirrors that alternately charge and discharge an external capacitor to generate an extremely linear sawtooth oscillator waveform. At the start of each cycle, the charging current, set by the choice of resistor at the Rset pin, is 1:1 mirrored over to the Cset pin where it charges an external capacitor. When the capacitor voltage reaches the comparator's upper threshold (nominally VREF), the comparator switches current mirrors and begins to discharge the external capacitor. The discharge current is set at roughly five times the charging current to result in fast discharge and minimal Dead Time. When the voltage reaches the comparator's lower threshold (0.9V), the comparator switches back to the charging mirror, powers down the discharge mirror, and the whole process repeats. The frequency is set by choosing Rset and Cset such that:
1 F OSC ----------------------------------------------0.84 x R SET x C SET
20KHz F OSC 1MHz
Suggested Ranges for Cset and Rset are: 50K ohms < Rset < 300K 10pf < Cset < 600pF
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320K 300K 280K 260K 240K 220K
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100pF
Rset 6 Cset 7 Rt
Ct
GND 12
390pF
200pF 200pF
47pF
20pF
10pF
RSET 200K
180K 160K 140K 120K 100K 80K 60K 40K 10K 100K 1M
Frequency Hz
FIGURE 3 - Timing Resistance vs Frequency
SCD5031 Rev B
8
Dead Time
The amount of dead time determines the maximum duty cycle that can be achieved. The Dead Time and the frequency of operation will determine the duty cycle.
Dead Time = 5280 ( C set + 12pF )
Dead Time Duty Cycle = 1 - ---------------------------- 1F osc
Selecting Rset and Cset
To select values for Rset and Cset perform the following steps to insure the smallest Dead Time.. 1) Determine what frequency is required for your design. 2) Use Figure 4 to select a capacitor value for Cset that will provide the highest duty cycle (shortest Dead Time) at the frequency required. 3) Calculate the value of Rset using the formula:
1 R set = ---------------------------------------.84 x F osc x C set
Note small values of Rset increase power consumption for the PWM5031 and small values of Cset may make PCB and stray capacitance a source of error.
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47pF 20pF
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100
98
390pF
200pF
100pF
96
10pF Duty Cycle %
94
92
90
88
86 10K 100K 1M
Frequency Hz
FIGURE 4 - Duty Cycle vs Frequency
SCD5031 Rev B
9
If desired, the user can synchronize the oscillator to an external frequency source by coupling a pulse train to the Cset pin:
Sync Pulse 2nF 24 Cset To PWM
FIGURE 5 - PWM can be synchronized to external source with just two additional components.
Operation is similar to the free running case. Cset is alternately charged and discharged by the same current mirrors and the same comparator and thresholds are used. The only difference is that when a sync pulse is received, the capacitor voltage is level shifted up and reaches the comparator's upper threshold voltage before it normally would in the free running case. If a series of pulses are received with shorter period than that of the free running oscillator, the comparator will trip in response to the sync pulse and the oscillator will be synchronized. (NOTE: The user must ensure that the sync pulse does not induce a voltage on CSET that exceeds the PWM5031 voltage rating. If this cannot be guaranteed, a simple diode clamp to the positive rail should be used to prevent damage to the PWM)
ERROR AMPLIFIER
The main error amplifier is a N-type input folded cascode configuration with a few interesting additions. The positive input is internally tied to 2.5V derived from the on chip reference. The negative input typically draws less than 1A and has a voltage offset of less than 2mV. At 20A bias current, the amplifier exceeds 2MHz bandwidth and 120dB open loop gain (see Figure 7). The amplifier is designed to limit at whatever voltage is applied to the SOFT pin. As mentioned previously, this function will allow the user to implement a softstart circuit, a controlled turn-on delay, or any number of other useful functions.
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SCD5031 Rev B
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10
VSOFT 10 2.5V Error Amp 1.4V COMP CURRENT SENSE GND 1V
2R R Current Sense Comparators S R Q Q
VFB IS R RS C
2 8
11
12
Peak Current (Is) is determined by the formula: I S MAX
=
1.0V ----------RS
or
I S MAX
=
V SOFT - 1.4 -------------------------------3R S
A small RC filter may be required to suppress switch transients
FIGURE 6 - Current Sense Circuit
120
80
-55C Gain dB
40
0
-40 1 10
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100 1K 11
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+125C
10K 100K 1M 10M
Frequency Hz
FIGURE 7 - Error Frequency Amplifier Open-Loop Response at +125C & -55C
SCD5031 Rev B
OUTPUT DRIVE
Dual push-pull outputs OutA and OutB are provided for driving off chip switches. The output stages are identical: Totem Pole configuration Break-before-make switching to prevent harmful cross-conduction spikes Separate positive and negative supply connections to decouple power stage and sensitive logic Near rail-to-rail voltage swing 1A maximum peak current capability (capacitive load) The outputs have two modes of control depending on whether the 50% toggle option is selected. In the case where the 50% pin is logic low, the outputs are in-phase with each other and the duty cycle is free to take on any value up to 100%. However, when the 50% pin is asserted high (logic ''1''), the outputs switch from the in-phase condition to the logical complement (out-of-phase) of each other and the duty cycle is limited to a maximum of 50%.
.30
.25
Sink Voltage V
.20
.15
Source
.10
.05
0 1 10 100
Current mA
FIGURE 8 - Output Saturation Characteristics at +25C
AUXILIARY AMPLIFIER
The chip includes an uncommitted op-amp with independent shutdown feature for use in any user-defined application. Some possibilities are: Signal conditioning of an isolated configuration feedback voltage Implementation of more sophisticated compensation networks for control loop optimization The Auxiliary amplifier has a unity gain bandwidth greater than 1MHz and an open loop gain greater than 100dB. The ENAUX pin is active high such that a logic ''1'' enables the amplifier and logic ''0'' disables it. The amplifier has near rail-to-rail capability on both the input and output.
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SCD5031 Rev B
12
TYPICAL APPLICATIONS
+5VDC
T1 3.3V, 0.5A
VCC EN DRVP Out A Out B VREF ISENSE 0.1F C1 RSOFT 50%
M1
R1
Rs
SOFT COMP M2 CSOFT Isolation Barrier
Cset Optional circuit to force zero duty cycle CSET Rset VFB Opto-Isolator or Pulse Transformer RSET VEE DRVN
FIGURE 9 - Typical Forward Converter Application
A typical single output forward converter application is shown in Figure 9 to aid in the following operational description. During normal operation, the oscillator jumpstarts each switching cycle by resetting the RS latch, causing the output stage to go high and turn on M1. Current begins to build linearly through T1 and M1 and a proportional voltage is developed across the small sense resistor Rs. Switching spikes are filtered by C1 and R1, and the resulting sawtooth waveform is passed into the PWM to serve as the current comparator input. Meanwhile, a portion of the output voltage is sensed and compared to the PWM's internal precision 2.5V reference. The difference is then amplified and level shifted to serve as the comparator threshold. When the voltage on the ISENSE pin exceeds this threshold, the comparator fires and resets the latch. The output then turns off until the beginning of the next oscillator cycle when the process repeats. Like all current mode PWMs, the chip provides built in fault protection by limiting peak switch current on a cycle by cycle basis. When an overload condition occurs, the sensed current reaches the current trip threshold earlier in the switching cycle than it otherwise would and thus forces the PWM latch off until the start of the next cycle. The process repeats until the overload condition is removed and the PWM can return to a normal duty cycle. The chip is capable of operating in this mode indefinitely without sustaining damage. There are two ways to set the current limit trip point. One is to simply tailor the sense resistor Rs:
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I pk = 1.0Vdc -----------------Rs
Some users may find the power is dissipated in Rs to be unacceptably high. In this case, the user can fix Rs at a small value and vary the current comparator threshold instead. Fortunately, the PWM chip provides a very convenient method for doing so. Because the error amplifier output is internally clamped to the SOFT pin, the user need simply apply the desired voltage level to the SOFT pin to arbitrarily lower the current comparator threshold.
SCD5031 Rev B
Recalling that the EA output is level shifted and divided before being applied to the comparator input, the peak current limit is chosen by applying a voltage VSOFT such that:
V soft - 1.4 I pk = -----------------------3 x Rs
1.4V V soft 4.4V
Clamping the EA output to the soft pin also makes implementing a softstart ciruit easy. Rsoft and Csoft are connected as in Figure 9 to provide the SOFT pin an asymptotically rising voltage. Because of the internal clamp on the EA output, the PWM duty cycle will increase only as fast as the chosen time constant will allow. In this way, excessive duty cycle and surge currents into the output capacitors are avoided. A transistor may be optionally connected across the softstart capacitor to force zero duty cycle on command. This is a particularly convenient method for implementing an externally controlled turn-on delay. The discussion so far assumes the user operates the chip in the current mode: switch current is sensed and compared to the error between the output voltage and a precision reference. Alternatively, the user may wish to implement voltage mode control in which the control loop is dependent only on the output voltage. The PWM chip readily supports this configuration with the following modification:
Switch Current
M1 Out Isense Vref 2N2222
Cset Cset
FIGURE 10 - Circuit for implementing voltage mode control.
A portion of the oscillator's sawtooth waveform is coupled to the ISENSE pin and becomes the input to the comparator stage. The operation is now identical to the current mode application: when the sawtooth voltage exceeds the amplified difference between the output and a voltage reference, the comparator fires and latches off the output until the start of the next cycle.
SELECTED APPLICATION EXAMPLES
The flexibility and performance of the chip makes it suitable for an enormous range of power converter applications - step-up, step-down, DC-DC, AC-DC, isolated/non-isolated, and many more. This section will cover two of the more popular power converter applications for which this chip is particularly well suited although many more can be envisioned.
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5V Input, 3.3V Isolated Output (Single Ended Forward Converter)
The isolated step down DC/DC converter is a staple of many satellite and aerospace systems. A common bus distributes raw primary power to various system loads which must then convert the primary to one or more low voltage secondary outputs. These outputs are filtered, regulated, and ground isolated from the primary side to keep EMI and undesired subsystem interaction at a minimum. Figure 9 is one example of a circuit that very efficiently performs this conversion. The values here were chosen to work for a 5V input and 3.3V output but the circuit topology is general enough to support an infinite variety of applications. For example, output voltages can be adjusted by changing values of just a few components. A wider input voltage range can be supported by varying the transformer's turns ratios and by proper selection of M1. Thus, a very wide range of power converter applications can be satisfied by simple variations of the circuit. At the start of each switching cycle, the PWM output goes high and turns on M1. Energy is coupled across T1's turns ratios to the secondary side where it is caught, rectified, and filtered to produce a clean DC voltage. A sampling network on the output side feeds back a portion of the output across the isolation barrier into the error amplifier negative input.
SCD5031 Rev B
14
This feedback can be accomplished in a number of different ways: pulse transformers, optocouplers, or capacitive coupling are a few methods. The compensation network may need modification depending on the feedback method chosen. The additional winding and rectifier on T1 are used to reset the transformer core after the PWM latches off M1 to prevent staircase saturation of the core. Note the chip is powered directly from the main power bus (via a zener and current limit resistor) without the need for additional bootstrap transformer windings. This is one of the main advantages this PWM chip provides over other products. This scheme could not be implemented with other chips which draw significantly more current. On the other hand, supplying bias to our PWM chip is about as simple as it gets.
5V to 1.8V Synchronous Buck Converter
A second application is a secondary side, non-isolated synchronous buck converter. The circuit takes a high voltage (5V in this case) and steps down to a lower voltage (5V to 1.8V in this example, although as pointed out above, these values are completely adjustable with proper component selection). The distinguishing feature of this implementation is the synchronous rectification scheme used to replace the standard Schottky rectifiers for more efficient power conversion of low voltage outputs.
INPUT 5V
VCC VREF RSOFT 0.1F CSOFT SOFT
DRVP
M1 Out A OUTPUT 1V/1.8V/2.5V/3.3V D1
CSET CSET RSET RSET ISENSE 50% Ccomp VFB VEE DRVN COMP Rcomp
FIGURE 11 - Buck Converter
The circuit switches M1 twice per cycle, chopping the 5VDC input into a fixed frequency pulse train whose DC average is the desired output voltage. The LC filter then simply smoothes this pulse train to produce a clean DC output. The control loop regulates against operating point perturbations (temperature, line, load) by adjusting M1's duty cycle. The circuit is operated in the voltage mode since switch current is not referenced to circuit ground. Alternatively, a current transformer may be used to properly reference the ISENSE signal to permit current mode control. An inverter is needed in the output path to properly drive the P-channel MOSFET. For low current applications (less than -50mA output current), it may be possible to use the PWM's output drive stage as the switching elements and eliminate M1 and D1 altogether.
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SCD5031 Rev B
15
VCC 1 50% 2
24 VCC 23 DRVP 22 DRVP 21 OUTA 20 OUT B 19 DRVN 18 DRVN 17 EN 16 ENAUX 15 A OUT 14 PIN 13 NIN
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SLEEP 3 COMP 4 VFB 5 ISENSE 6 SOFT 7 CSET 8 RSET 9 PWROK 10 VREF 11 VEE 12
FIGURE 12 - Package Pin vs Function
SCD5031 Rev B
16
CONFIGURATIONS AND ORDERING INFORMATION
MODEL NO. PWM5031-7 PWM5031-I PWM5031-S 25A4524 (Die) SCREENING 1/ Class C Class I Space Applications 2/ Die Size - .125L x .117W inch CASE Flat Package
1. Level of screening - Class C = Commercial Flow, Commercial Temp. Range, 0C to +70C testing; Class I = Commercial Flow, Industrial Temp. Range, -40C to +85C testing; Space Applications = Military Temp. Range, Screened to the individual test methods of MIL-STD-883, -55C to +125C testing. 2. Each die shall be 100% visually inspected to assure conformance with the applicable die related requirements of MIL-STD-883, method 2010, cond A or cond B.
PIN 1
.394 .419 .300 MAX PIN 24 11 x .050 = .550 .006
.614 MAX .019 .015
.130 MAX .030 REF .008 .0012 .022 .005 .012 MAX .335 MIN .354 REF
FIGURE 13 - Flat Package Configuration Outline
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www.aeroflex.com
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Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied.
SCD5031 Rev B 8/2/05
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